This book provides a comprehensive review of the state-of-the-art in the development of new and innovative materials, and of advanced modeling and characterization methods for nanoscale CMOS devices.
Leading global industry bodies including the International Technology Roadmap for Semiconductors (ITRS) have created a forecast of performance improvements that will be delivered in the foreseeable future – in the form of a roadmap that will lead to a substantial enlargement in the number of materials, technologies and device architectures used in CMOS devices.
This book addresses the field of materials development, which has been the subject of a major research drive aimed at finding new ways to enhance the performance of semiconductor technologies. It covers three areas that will each have a dramatic impact on the development of future CMOS devices: global and local strained and alternative materials for high speed channels on bulk substrate and insulator; very low access resistance; and various high dielectric constant gate stacks for power scaling.
The book also provides information on the most appropriate modeling and simulation methods for electrical properties of advanced MOSFETs, including ballistic transport, gate leakage, atomistic simulation, and compact models for single and multi-gate devices, nanowire and carbon-based FETs. Finally, the book presents an in-depth investigation of the main nanocharacterization techniques that can be used for an accurate determination of transport parameters, interface defects, channel strain as well as RF properties, including capacitance-conductance, improved split C-V, magnetoresistance, charge pumping, low frequency noise, and Raman spectroscopy.
PART 1. NOVEL MATERIALS FOR NANOSCALE CMOS
1. Introduction to Part 1, D. Leadley, A. Dobbie, V. Shah AND J. Parsons.
2. Gate Stacks, O. Engström, I. Z. Mitrovic, S. Hall, P. K. Hurley, K. Cherkaoui, S. Monaghan, H. D. B. Gottlob and M. C. Lemme.
3. Strained Si and Ge Channels, D. Leadley, A. Dobbie, M. Myronov, V. Shah and E. Parker.
4. From Thin Si/SiGe Buffers to SSOI, S. Mantl and D. Buca.
5. Introduction to Schottky-Barrier MOS Architectures: Concept, Challenges, Material Engineering and Device Integration, E. Dubois, G. Larrieu, R Valentin, N. Breil and F. Danneville.
PART 2. ADVANCED MODELING AND SIMULATION FOR NANO-MOSFETS AND BEYOND-CMOS DEVICES
6. Introduction to Part 2, E. Sangiorgi.
7. Modeling and Simulation Approaches for Gate Current Computation, B. Majkusiak, P. Palestri, A. Schenk, A. S. Spinelli, C. M. Compagnoni and M. Luisier.
8. Modeling and Simulation Approaches for Drain Current Computation, M. Vasicek, D. Esseni, C. Fiegna and T. Grasser.
9. Modeling of End of the Roadmap nMOSFET with Alternative Channel Material, Q. Rafhay, R. Clerc, G. Ghibaudo, P. Palestri and L. Selmi.
10. NEGF for 3D Device Simulation of Nanometric Inhomogeneities, A. Martinez, A. Asenov and M. Pala.
11. Compact Models for Advanced CMOS Devices, B. Iñiguez, F. Lime, A. Lázaro and T. A. Fjeldly.
12. Beyond CMOS, G. Iannaccone, G. Fiori, S. Reggiani and M. Pala.
PART 3. NANOCHARACTERIZATION METHODS
13. Introduction to Part 3, D. Flandre.
14. Accurate Determination of Transport Parameters in Sub-65 nm MOS Transistors, M. Mouis and G. Ghibaudo.
15. Characterization of Interface Defects, P. Hurley, O. Engström, D. Bauza and G. Ghibaudo.
16. Strain Determination, A. O’Neill, S. Olsen, P. Dobrosz, R. Agaiby and Y. Tsang.
17. Wide Frequency Band Characterization, D. Flandre, J.-P. Raskin and V. Kilchytska.
Francis Balestra is Director of the Laboratoire de Physique des Composants à Semiconducteurs (LPCS) at INP Grenoble in France. He has co-authored over 80 publications in international scientific journals and 120 communications at national and international conferences (20 invited papers and review articles).
Table of Contents
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