Plasma etching has long enabled the perpetuation of Moore's Law. Today, etch compensation helps to create devices that are smaller than 20 nm. But, with the constant downscaling in device dimensions and the emergence of complex 3D structures (like FinFet, Nanowire and stacked nanowire at longer term) and sub 20 nm devices, plasma etching requirements have become more and more stringent.
Now more than ever, plasma etch technology is used to push the limits of semiconductor device fabrication into the nanoelectronics age. This will require improvement in plasma technology (plasma sources, chamber design, etc.), new chemistries (etch gases, flows, interactions with substrates, etc.) as well as a compatibility with new patterning techniques such as multiple patterning, EUV lithography, Direct Self Assembly, ebeam lithography or nanoimprint lithography.
This book presents these etch challenges and associated solutions encountered throughout the years for transistor realization.
1. CMOS Devices Through the Years by Maud Vinet and Nicolas Posseme
2. Plasma Etching in Microelectronics by Maxime Darnon
3. Patterning Challenges in Microelectronics by Sébastien Barnola, Nicolas Posseme, Stefan Landis and Maxime Darnon
4. Plasma Etch Challenges for Gate Patterning by Maxime Darnon and Nicolas Posseme
Nicolas Posseme is a senior research scientist in micro and nanotechnology and deputy head of plasma etching & stripping in the silicon technologies division at the CEA-LETI Laboratory in Grenoble, France.
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