Multi-Processor System-on-Chip 1


Architectures


SCIENCES – Electronics Engineering

Multi-Processor System-on-Chip 1

Edited by

Liliana Andrade, Université Grenoble Alpes, France
Frédéric Rousseau, Université Grenoble Alpes, France


ISBN : 9781789450217

Publication Date : May 2021

Hardcover 316 pp

165.00 USD

Co-publisher

Description


A Multi-Processor System-on-Chip (MPSoC) is the key component for complex applications. These applications put huge pressure on memory, communication devices and computing units. This book, presented in two volumes – Architectures and Applications – therefore celebrates the 20th anniversary of MPSoC, an interdisciplinary forum that focuses on multi-core and multi-processor hardware and software systems. It is this interdisciplinarity which has led to MPSoC bringing together experts in these fields from around the world, over the last two decades.

Multi-Processor System-on-Chip 1 covers the key components of MPSoC: processors, memory, interconnect and interfaces. It describes advance features of these components and technologies to build efficient MPSoC architectures. All the main components are detailed: use of memory and their technology, communication support and consistency, and specific processor architectures for general purposes or for dedicated applications.

Contents


Part 1. Processors
1. Processors for the Internet of Things, Pieter Van Der Wolf and Yankin Tanurhan.
2. A Qualitative Approach to Many-core Architecture, Benoît Dupont DE Dinechin.
3. The Plural Many-core Architecture – High Performance at Low Power, Ran Ginosar.
4. ASIP-Based Multi-Processor Systems for an Efficient Implementation of CNNs, Andreas Bytyn, René Ahlsdorf and Gerd Ascheid.

Part 2. Memory
5. Tackling the MPSoC Data Locality Challenge, Sven Rheindt, Akshay Srivatsa, Oliver Lenke, Lars Nolte,
Thomas Wild and Andreas Herkersdorf.
6. mMPU: Building a Memristor-based General-purpose In-memory Computation Architecture, Adi Eliahu, Rotem Ben Hur, Ameer Haj Ali and Shahar Kvatinsky
7. Removing Load/Store Helpers in Dynamic Binary Translation, Antoine Faravelon, Olivier Gruber and Frédéric Pétrot.
8. Study and Comparison of Hardware Methods for Distributing Memory Bank Accesses in Many-core Architectures, Arthur Vianes and Frédéric Rousseau.

Part 3. Interconnect and Interfaces
9. Network-on-Chip (NoC): The Technology that Enabled Multi-processor Systems-on-Chip (MPSoCs), K. Charles Janac.
10. Minimum Energy Computing via Supply and Threshold Voltage Scaling, Jun Shiomi and Tohru Ishihara.
11. Maintaining Communication Consistency During Task Migrations in Heterogeneous Reconfigurable Devices, Arief Wicaksana, Olivier Muller, Frédéric Rousseau and Arif Sasongko.

About the authors


Liliana Andrade is Associate Professor at TIMA Lab, Université Grenoble Alpes in France. She received her PhD in Computer Science, Telecommunications and Electronics from Université Pierre et Marie Curie in 2016. Her research interests include system-level modeling/validation of systems-on-chips, and the acceleration of heterogeneous systems simulation.

Frédéric Rousseau is Full Professor at TIMA Lab, Université Grenoble Alpes in France. His research interests concern Multi-Processor Systems-on-Chip design and architecture, prototyping of hardware/software systems including reconfigurable systems and high-level synthesis for embedded systems.