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Wall Turbulence Control

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From Photon to Pixel – Revised and Updated 2nd Edition

The Digital Camera Handbook

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Fluid–Structure Interactions and Uncertainties

Ansys and Fluent Tools

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Stochastic Analysis of Risk and Management

Stochastic Models in Survival Analysis and Reliability Set – Volume 2

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Musical Techniques

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Location Strategies and Value Creation of International Mergers and Acquisitions

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Current and Emerging Issues in the Audiovisual Industry

Diverse and Global Perspectives on Value Creation Set – Volume 1

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International Specialization Dynamics

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Reflexive Governance for Research and Innovative Knowledge

Responsible Research and Innovation Set – Volume 6

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Reliability Investigation of LED Devices for Public Light Applications

Durability, Robustness and Reliability of Photonic Devices Set

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Plasma Etching Processes for CMOS Device Realization

Edited by Nicolas Posseme, CEA-LETI Laboratory, Grenoble, France

ISBN: 9781785480966

Publication Date: January 2017   Hardback   136 pp.

80 USD


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Description

Plasma etching has long enabled the perpetuation of Moore's Law. Today, etch compensation helps to create devices that are smaller than 20 nm. But, with the constant downscaling in device dimensions and the emergence of complex 3D structures (like FinFet, Nanowire and stacked nanowire at longer term) and sub 20 nm devices, plasma etching requirements have become more and more stringent.
Now more than ever, plasma etch technology is used to push the limits of semiconductor device fabrication into the nanoelectronics age. This will require improvement in plasma technology (plasma sources, chamber design, etc.), new chemistries (etch gases, flows, interactions with substrates, etc.) as well as a compatibility with new patterning techniques such as multiple patterning, EUV lithography, Direct Self Assembly, ebeam lithography or nanoimprint lithography.
This book presents these etch challenges and associated solutions encountered throughout the years for transistor realization.

Contents

1. CMOS Devices Through the Years by Maud Vinet and Nicolas Posseme
2. Plasma Etching in Microelectronics by Maxime Darnon
3. Patterning Challenges in Microelectronics by Sébastien Barnola, Nicolas Posseme, Stefan Landis and Maxime Darnon
4. Plasma Etch Challenges for Gate Patterning by Maxime Darnon and Nicolas Posseme

About the Authors

Nicolas Posseme is a senior research scientist in micro and nanotechnology and deputy head of plasma etching & stripping in the silicon technologies division at the CEA-LETI Laboratory in Grenoble, France.

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