Publication Date: December 2013 Hardback 192 pp.
Computer systems are becoming more and more powerful and, in parallel, more and more complex. Even though increased computing performance is at the core of these developments, the complexity raises major challenges, especially in the domain of hard real-time systems. These systems need to provide a deterministic timing behavior, since unpredictable variations of timing can lead to catastrophic results.
Time-Predictable Architectures is concerned with building computers that can be used to design embedded real-time systems. Real-time embedded software requires increasingly higher performances, which leads the authors to consider processors that implement advanced mechanisms such as pipelining, out-of-order execution, branch prediction, cache memories, multithreading, multicore architectures, etc. The authors investigate the time-predictability of such schemes. This book mainly deals with hard real-time systems where it is expected that no failure occurs during the time that the system is effective (often referred to as the time of the mission in reference to aeronautics and space systems).
This book is aimed at processor architects and software developers with the intention of raising awareness of timing challenges. Engineers in aeronautics and researchers on WCET analysis will also benefit from this book.
1. Real-Time Systems and Time Predictability.
2. Timing Analysis of Real-Time Systems.
3. Current Processor Architectures.
4. Memory Hierarchy.
6. Example Architectures.
About the Authors
Christine Rochange is Professor at Paul Sabatier University in Toulouse, France. She is conducting research activities in the TRACES group at the Institut de Recherche en Informatique de Toulouse (IRIT lab). Her current research interests include the analysis of worst-case execution times of sequential and parallel real-time applications.
Sascha Uhrig is a Junior Professor leading the Microcontroller Systems group at the Department of Electrical Engineering and Information Technology at the Technical University of Dortmund, Germany. His research interests concern processor and computer architecture with the focus on time-predictable architectures. He is working on multithreaded as well as multicore processors, including memory hierarchies.
Pascal Sainrat is Professor at Paul Sabatier University in Toulouse, France. He is the leader of the TRACES group at the Institut de Recherche en Informatique de Toulouse (IRIT lab) and his current research interests concern the design of time-predictable architectures.